clk: starfive: Change divider value of cpu_core clock
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 15 Dec 2022 06:17:59 +0000 (14:17 +0800)
committerXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 15 Dec 2022 06:18:05 +0000 (14:18 +0800)
commit25fbb716f1aefafb731082d5d571ea040d5d51a4
tree7f76e7702173480749ba73f71ebe61205ea061ff
parent5e6efe042c857d736ac3c3d47df0afe684733832
clk: starfive: Change divider value of cpu_core clock

Change divider value to make sure the frequency is half of PLL0.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-gen.c