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[RISCV] Without Zfh, promote f16 inputs before creating RISCVISD::FCVT_W(U)_RV64...
authorCraig Topper <craig.topper@sifive.com>
Wed, 7 Dec 2022 20:25:30 +0000 (12:25 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 7 Dec 2022 20:25:30 +0000 (12:25 -0800)
commit258bb453fb84b2f149a51adf9ebfd535f4288fe2
treed2102fc19132f0cd16900d8a4fe6477d16495aa3tree | snapshot
parent92e54b09ce076a9e5e109d52e4fff6b1530dcb7acommit | diff
[RISCV] Without Zfh, promote f16 inputs before creating RISCVISD::FCVT_W(U)_RV64 nodes.

This allows us to remove a couple more Zfhmin isel patterns.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td diff | blob | history
Domain: System / Toolchain;