powerpc/xive: Fix offset for store EOI MMIOs
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 14 Jun 2017 00:19:25 +0000 (10:19 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Thu, 15 Jun 2017 13:29:39 +0000 (23:29 +1000)
commit25642705b2359a705784bbbf1655c25a8f8efde2
tree9bf28359bbc21c224f1eabdb3a6fce68e4eb271c
parent377aa6b0efbaa29cfeecd8b9244641217f9544ca
powerpc/xive: Fix offset for store EOI MMIOs

Architecturally we should apply a 0x400 offset for these. Not doing
it will break future HW implementations.

The offset of 0 is supposed to remain for "triggers" though not all
sources support both trigger and store EOI, and in P9 specifically,
some sources will treat 0 as a store EOI. But future chips will not.
So this makes us use the properly architected offset which should work
always.

Fixes: 243e25112d06 ("powerpc/xive: Native exploitation of the XIVE interrupt controller")
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/include/asm/xive.h
arch/powerpc/kvm/book3s_xive_template.c
arch/powerpc/sysdev/xive/common.c