[ARM GlobalISel] 64-bit memops should be aligned
authorDiana Picus <diana.picus@linaro.org>
Mon, 25 Mar 2019 08:54:29 +0000 (08:54 +0000)
committerDiana Picus <diana.picus@linaro.org>
Mon, 25 Mar 2019 08:54:29 +0000 (08:54 +0000)
commit254b11a0fd864ab42eef2d6cf781330959c58567
tree103034fadbed594c5b778b6828e01c4ab2058ad0
parentd8e78022c63b9fc9af6260eef667231c929e9cee
[ARM GlobalISel] 64-bit memops should be aligned

We currently use only VLDR/VSTR for all 64-bit loads/stores, so the
memory operands must be word-aligned. Mark aligned operations as legal
and narrow non-aligned ones to 32 bits.

While we're here, also mark non-power-of-2 loads/stores as unsupported.

llvm-svn: 356872
llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir