PCI: qcom: Fix the incorrect register usage in v2.7.0 config
authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thu, 16 Mar 2023 08:10:59 +0000 (13:40 +0530)
committerLorenzo Pieralisi <lpieralisi@kernel.org>
Tue, 11 Apr 2023 09:31:10 +0000 (11:31 +0200)
commit2542e16c392508800f1d9037feee881a9c444951
treea33078b80748b61854469fa5602a0b78a3e9a64b
parentfe15c26ee26efa11741a7b632e9f23b01aca4cc6
PCI: qcom: Fix the incorrect register usage in v2.7.0 config

Qcom PCIe IP version v2.7.0 and its derivatives don't contain the
PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT register. Instead, they have the new
PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register. So fix the incorrect
register usage which is modifying a different register.

Also in this IP version, this register change doesn't depend on MSI
being enabled. So remove that check also.

Link: https://lore.kernel.org/r/20230316081117.14288-2-manivannan.sadhasivam@linaro.org
Fixes: ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: <stable@vger.kernel.org> # 5.6+
drivers/pci/controller/dwc/pcie-qcom.c