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(parent: f3d1a1a) | patch
AMDGPU: Fix spilling of m0
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 3 Sep 2016 06:57:55 +0000 (06:57 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 3 Sep 2016 06:57:55 +0000 (06:57 +0000)
commit2510a316773cb7128554bcecc8d209abef326c78
treeacad5a8f18ca6ff6e267440e7a0a9bfac3af86b6tree | snapshot
parentf3d1a1a1b6b57e6030f0719c358fa08f25558013commit | diff
AMDGPU: Fix spilling of m0

readlane/writelane do not support using m0 as the output/input.
Constrain the register class of spill vregs to try to avoid this,
but also handle spilling of the physreg when necessary by inserting
an additional copy to a normal SGPR.

llvm-svn: 280584
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIInstructions.td diff | blob | history
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/m0-spill.ll [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/spill-m0.ll [new file with mode: 0644] blob
Domain: System / Toolchain;