[arm] Reduce cost of insns that are simple reg-reg moves.

[arm] Reduce cost of insns that are simple reg-reg moves.

Consider this sequence during combine:

Trying 18, 7 -> 22:
   18: r118:SI=r122:SI
      REG_DEAD r122:SI
    7: r114:SI=0x1-r118:SI-ltu(cc:CC_RSB,0)
      REG_DEAD r118:SI
      REG_DEAD cc:CC_RSB
   22: r1:SI=r114:SI
      REG_DEAD r114:SI
Failed to match this instruction:
(set (reg:SI 1 r1 [+4 ])
    (minus:SI (geu:SI (reg:CC_RSB 100 cc)
            (const_int 0 [0]))
        (reg:SI 122)))
Successfully matched this instruction:
(set (reg:SI 114)
    (geu:SI (reg:CC_RSB 100 cc)
        (const_int 0 [0])))
Successfully matched this instruction:
(set (reg:SI 1 r1 [+4 ])
    (minus:SI (reg:SI 114)
        (reg:SI 122)))
allowing combination of insns 18, 7 and 22
original costs 4 + 4 + 4 = 12
replacement costs 8 + 4 = 12

The costs are all correct, but we really don't want this combination
to take place.  The original costs contain an insn that is a simple
move of one pseudo register to another and it is extremely likely that
register allocation will eliminate this insn entirely.  On the other
hand, the resulting sequence really does expand into a sequence that
costs 12 (ie 3 insns).

We don't want to prevent combine from eliminating such moves, as this
can expose more combine opportunities, but we shouldn't rate them as
profitable in themselves.  We can do this be adjusting the costs
slightly so that the benefit of eliminating such a simple insn is
reduced.

We only do this before register allocation; after allocation we give
such insns their full cost.

	* config/arm/arm.c (arm_insn_cost): New function.
	(TARGET_INSN_COST): Override default definition.

From-SVN: r277174