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[X86][AVX] Ensure chained subvector insertions are the same size (PR42833)
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 31 Jul 2019 12:55:39 +0000 (12:55 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 31 Jul 2019 12:55:39 +0000 (12:55 +0000)
commit24ad2b5e7d8ceecb045bfc499107b9ed90439adb
treeccecf7fb87e76b58d171ad4fbabe2a6da14f7c44tree | snapshot
parenta36d31478c182903523e04eb271bbf102bfab2cccommit | diff
[X86][AVX] Ensure chained subvector insertions are the same size (PR42833)

Before combining insert_subvector(insert_subvector(vec, sub0, c0), sub1, c1) patterns, ensure that the subvectors are all the same type. On AVX512 targets especially we might have a mixture of 128/256 subvector insertions.

llvm-svn: 367429
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/oddsubvector.ll diff | blob | history
Domain: System / Toolchain;