spi: cadence_qspi: Enable apb linear mode for apb read & write operations
authorT Karthik Reddy <t.karthik.reddy@xilinx.com>
Thu, 12 May 2022 10:05:34 +0000 (04:05 -0600)
committerMichal Simek <michal.simek@amd.com>
Wed, 29 Jun 2022 14:00:31 +0000 (16:00 +0200)
commit248fe9f302df5f20d75a7d88b793db017262d750
tree642dc7f671ce7af7deca3a61857a43c5c60e38f5
parentbf8dae5fcf400a593d56d5847d8ee62bc4c27855
spi: cadence_qspi: Enable apb linear mode for apb read & write operations

On versal platform, enable apb linear mode for apb read and write
execute operations amd disable it when using dma reads. This is done by
xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled,
else we use direct raw reads and writes in case of mini U-Boot.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
arch/arm/mach-versal/include/mach/hardware.h
drivers/spi/cadence_ospi_versal.c
drivers/spi/cadence_qspi.c
drivers/spi/cadence_qspi.h
drivers/spi/cadence_qspi_apb.c
include/zynqmp_firmware.h