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[SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to SimplifyDem...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 9 Oct 2018 13:13:35 +0000 (13:13 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 9 Oct 2018 13:13:35 +0000 (13:13 +0000)
commit23f880317a36459a3a5080da325233f4996820a9
tree003ef7054c615cdb52489bbdc2bfddd569ef8c71tree | snapshot
parentdaf662c492bdfed875eeac9e499642d994492022commit | diff
[SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to SimplifyDemandedBits

Fix for AVX1 masked load/store regression on D52964

llvm-svn: 344043
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/vselect-avx.ll diff | blob | history
Domain: System / Toolchain;