misc: hpilo: map iLO shared memory by PCI revision id

misc: hpilo: map iLO shared memory by PCI revision id

Starting from iLO ASIC 'Neches' with subsystem device id 0x00E4,
bar 5 is used for shared memory region mapping instead of bar 2
because bar 2 is made inaccessible after system POST for security
reason.

As this holds true for future iLO ASIC generations, it does not
make sense to map shared memory region according to the subsystem
device id of each following generations.

Map iLO shared memory region with PCI revision id that maps to the
iLO ASIC generation, starting from Neches (Rev 7).

Signed-off-by: Matt Hsiao <matt.hsiao@hpe.com>
Link: https://lore.kernel.org/r/20210531085551.26421-1-matt.hsiao@hpe.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>