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(parent: 61c9b7a) | patch
intel/nir/rt: add a new number of SIMD lanes per DSS helper
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Mon, 21 Jun 2021 10:56:32 +0000 (13:56 +0300)
committerMarge Bot <emma+marge@anholt.net>
Tue, 8 Feb 2022 12:55:24 +0000 (12:55 +0000)
commit23ce94ff7e28ee1771f53931d20c0ed1fe87c4a5
tree0dc45ce06531028ae50dffda06380c54d322bda6tree | snapshot
parent61c9b7a82e99892cfcd70fedb2a4fd3fdd795256commit | diff
intel/nir/rt: add a new number of SIMD lanes per DSS helper

v2: Add prefix brw_nir_rt (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
src/intel/compiler/brw_nir_rt_builder.h diff | blob | history
Domain: Graphics System / GL;