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(parent: 1dd65bb) | patch
clk: renesas: r9a09g011: Add eth clock and reset entries
authorPhil Edworthy <phil.edworthy@renesas.com>
Wed, 4 May 2022 14:54:46 +0000 (15:54 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 6 May 2022 07:38:40 +0000 (09:38 +0200)
commit23426d1be3c20907b4f3d72bf95234d4ee254393
tree2ec446e7cc89360c1d00315d51a112af86be1095tree | snapshot
parent1dd65bb08604ad2906d839c243e1bede2b0efe53commit | diff
clk: renesas: r9a09g011: Add eth clock and reset entries

Add ethernet clock/reset entries to CPG driver.

Note that the AXI and CHI clocks are both enabled and disabled using
the same register bit.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g011-cpg.c diff | blob | history
Domain: System / Kernel;