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(parent: 6e85f89) | patch
RISC-V: Fix RVV machine mode attribute configuration
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Wed, 14 Dec 2022 07:01:56 +0000 (15:01 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 19 Dec 2022 14:09:35 +0000 (22:09 +0800)
commit22dc669e109de9a76c74535cdf30e7922e0ef5c1
treee5929ec0e5d29465f14c020df1d9e44b30f5643ftree | snapshot
parent6e85f89a7d59a99a3395b6e153b99262a58b2f6ccommit | diff
RISC-V: Fix RVV machine mode attribute configuration

The attribute configuration of each machine mode are support in the previous patch.
I noticed some of them are not correct during VSETVL PASS testsing.
Correct them in the single patch now.

gcc/ChangeLog:

* config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes.
gcc/config/riscv/riscv-vector-switch.def diff | blob | history
Domain: System / Toolchain;