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(parent: f6d20e2) | patch
upstream: [media] mt9p031: Add support for PLL bypass
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Sun, 9 Feb 2014 20:31:47 +0000 (17:31 -0300)
committerChanho Park <chanho61.park@samsung.com>
Tue, 18 Nov 2014 02:58:45 +0000 (11:58 +0900)
commit225f9795bfa236c7aa03228eee69b7695bfa653e
treea47c00ecc36159154879f194c9ecc25d738d21d5tree | snapshot
parentf6d20e2127c88d1419c8d1e34d0f2d7d2f99776bcommit | diff
upstream: [media] mt9p031: Add support for PLL bypass

When the input clock frequency is out of bounds for the PLL, bypass the
PLL and just divide the input clock to achieve the requested output
frequency.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
drivers/media/i2c/mt9p031.c diff | blob | history
Domain: System / Kernel;