spicc: support irregular bit-width

spicc: support irregular bit-width

PD#162464: spicc: support irregular bit-width

some device work at a irregular bit-width for example,
11 bit-width and tx data is {0xa1, 0x62},
the LSB bit order is: 10100001 011 (0xa1 + 3 bits of 0x62)
the MSB bit order is: 01100010 101 (0x62 + 3 bits of 0xa1)
note: all case more than 16 bits will run at 4-byte-per-word though one
byte discarded.

to print the difference between tx and rx if mode[16]=1

Change-Id: Ibdd438c3fe764986c71b77ec2d4fa0db489dd439
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>