net/mlx5: Expose IP-in-IP TX and RX capability bits
authorAya Levin <ayal@nvidia.com>
Fri, 20 Nov 2020 23:03:32 +0000 (15:03 -0800)
committerSaeed Mahameed <saeedm@nvidia.com>
Fri, 27 Nov 2020 02:43:48 +0000 (18:43 -0800)
commit21adf05d4584c99a07a604224b9cfeddcc6bc47c
tree0653a9b0387844f7654ef640290e5b87e3b7d8bd
parent349125ba232ea53d71a57c65c81f109c323cc369
net/mlx5: Expose IP-in-IP TX and RX capability bits

Expose FW indication that it supports stateless offloads for IP over IP
tunneled packets per direction. In some HW like ConnectX-4 IP-in-IP
support is not symmetric, it supports steering on the inner header but
it doesn't TX-Checksum and TSO. Add IP-in-IP capability per direction to
cover this case as well.

Note: only if both indications are turned on, the global
tunnel_stateless_ip_over_ip is on too.

Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
include/linux/mlx5/mlx5_ifc.h