MIPS: lantiq: Fix Danube USB clock
authorMathias Kresin <dev@kresin.me>
Fri, 16 Mar 2018 20:27:28 +0000 (21:27 +0100)
committerJames Hogan <jhogan@kernel.org>
Wed, 21 Mar 2018 21:57:29 +0000 (21:57 +0000)
commit214cbc14734958fe533916fdb4194f5983ad4bc4
tree218cafd7d04e573f1f0a1a1a2f2e6fa5ca007ac8
parent0c8efd610b58cb23cefdfa12015799079aef94ae
MIPS: lantiq: Fix Danube USB clock

On Danube the USB0 controller registers are at 1e101000 and the USB0 PHY
register is at 1f203018 similar to all other lantiq SoCs. Activate the
USB controller gating clock thorough the USB controller driver and not
the PHY.

This fixes a problem introduced in a previous commit.

Fixes: dea54fbad332 ("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module")
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.14+
Patchwork: https://patchwork.linux-mips.org/patch/18816/
Signed-off-by: James Hogan <jhogan@kernel.org>
arch/mips/lantiq/xway/sysctrl.c