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(parent: c81f784) | patch
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
authorXingyu Wu <xingyu.wu@starfivetech.com>
Mon, 17 Jul 2023 02:30:36 +0000 (10:30 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 19 Jul 2023 17:08:00 +0000 (18:08 +0100)
commit2110add84bc6e21a1bf55f2c9d1fc14d408ce2e0
treeb87058bc89d5efd3c1a8c7ef9e47c2d7723f41c3tree | snapshot
parentc81f7845b2ce7a2ea1beb2ac4621b5d568d2b644commit | diff
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

Add PLL clock inputs from PLL clock generator.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml diff | blob | history
Domain: System / Kernel;