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author	David Stuttard <david.stuttard@amd.com>
	Tue, 12 Mar 2019 09:52:58 +0000 (09:52 +0000)
committer	David Stuttard <david.stuttard@amd.com>
	Tue, 12 Mar 2019 09:52:58 +0000 (09:52 +0000)
commit	20ea21c6ede8426be9832d684409a2388e2ca31a
tree	f092654776b1fb81f341dc7fad60ebf668d4d0ed	tree \| snapshot
parent	31ff647c1d261364e716e6b607065b6ecce4ca1f	commit \| diff

[AMDGPU] Add support for immediate operand for S_ENDPGM

Summary:
Add support for immediate operand in S_ENDPGM

Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6

Reviewers: alexshap

Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59213

llvm-svn: 355902

99 files changed:

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInsertSkips.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInstrInfo.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SOPInstructions.td		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/endpgm-dce.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fold-multiple.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/global-load-store-atomics.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/hazard-kill.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/hazard.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory_clause.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/merge-load-store.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/misched-killflags.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mode-register.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/movrels-bug.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/v_swap_b32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir		diff \| blob \| history
llvm/test/MC/AMDGPU/s_endpgm.s	[new file with mode: 0644]	blob
llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir		diff \| blob \| history

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