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author	Fei Peng <fei.peng@intel.com>
	Tue, 4 Dec 2018 19:41:02 +0000 (11:41 -0800)
committer	Fei Peng <fei.peng@intel.com>
	Tue, 4 Dec 2018 19:41:02 +0000 (11:41 -0800)
commit	20d9b576a4603500305e0d15c9f2887229367432
tree	aa98204c4ffd900d1fe459ef0bf29ff66015ed40	tree \| snapshot
parent	790e8cd145ad53ca2d2938ffa3d15f94bd27e89b	commit \| diff

Remove redundant checks in test templates

Commit migrated from https://github.com/dotnet/coreclr/commit/86e6443684982ffd13f6cdfb4ead82f586063934

49 files changed:

src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1.X64/AndNot.UInt64.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1.X64/ExtractLowestSetBit.UInt64.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1.X64/GetMaskUpToLowestSetBit.UInt64.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1.X64/ResetLowestSetBit.UInt64.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1.X64/TrailingZeroCount.UInt64.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1/AndNot.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1/ExtractLowestSetBit.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1/GetMaskUpToLowestSetBit.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1/ResetLowestSetBit.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi1/TrailingZeroCount.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi2.X64/ParallelBitDeposit.UInt64.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi2.X64/ParallelBitExtract.UInt64.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi2/ParallelBitDeposit.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Bmi2/ParallelBitExtract.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Shared/ExtractScalarTest.template		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Shared/InsertScalarTest.template		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Shared/ScalarBinOpTest.template		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Shared/ScalarSimdUnOpTest.template		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Shared/ScalarUnOpTest.template		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse2/Extract.UInt16.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse2/Extract.UInt16.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse2/Insert.Int16.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse2/Insert.Int16.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse2/Insert.UInt16.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse2/Insert.UInt16.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Extract.Int64.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Extract.Int64.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Extract.UInt64.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Extract.UInt64.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Insert.Int64.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Insert.Int64.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Insert.UInt64.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41.X64/Insert.UInt64.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.Byte.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.Byte.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.Int32.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.Int32.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.Single.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.Single.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.UInt32.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Extract.UInt32.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Byte.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Byte.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Int32.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.Int32.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.SByte.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.SByte.129.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.UInt32.1.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/X86/Sse41/Insert.UInt32.129.cs		diff \| blob \| history

Domain: Dotnet / Core;

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