[llvm/CodeGen] Enable the ExpandLargeDivRem pass for X86, Arm and AArch64
authorMatthias Gehre <matthias.gehre@xilinx.com>
Tue, 19 Jul 2022 10:28:54 +0000 (11:28 +0100)
committerMatthias Gehre <matthias.gehre@xilinx.com>
Tue, 6 Sep 2022 14:32:04 +0000 (15:32 +0100)
commit2090e85fee9b2d2a1ca6402b5f44c7d41d1e353f
treeacde58342a0eb28242732536d13ed9dfa0fa9aba
parenta69404c0a294ce65432ce67d5f3e7dce28106496
[llvm/CodeGen] Enable the ExpandLargeDivRem pass for X86, Arm and AArch64

This adds the ExpandLargeDivRem to the default pass pipeline.
The limit at which it expands div/rem instructions is configured
via a new TargetTransformInfo hook (default: no expansion)
X86, Arm and AArch64 backends implement this hook to expand div/rem
instructions with more than 128 bits.

Differential Revision: https://reviews.llvm.org/D130076
23 files changed:
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/CodeGen/ExpandLargeDivRem.cpp
llvm/lib/CodeGen/TargetPassConfig.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.h
llvm/test/CodeGen/AArch64/O0-pipeline.ll
llvm/test/CodeGen/AArch64/O3-pipeline.ll
llvm/test/CodeGen/AArch64/udivmodei5.ll [new file with mode: 0644]
llvm/test/CodeGen/ARM/O3-pipeline.ll
llvm/test/CodeGen/ARM/udivmodei5.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/O0-pipeline.ll
llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
llvm/test/CodeGen/X86/i128-sdiv.ll
llvm/test/CodeGen/X86/i128-udiv.ll
llvm/test/CodeGen/X86/libcall-sret.ll [deleted file]
llvm/test/CodeGen/X86/opt-pipeline.ll
llvm/test/CodeGen/X86/pr38539.ll
llvm/test/CodeGen/X86/udivmodei5.ll [new file with mode: 0644]