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(parent: 5fb190b) | patch
iommu/io-pgtable-arm: Rationalise MAIR handling
authorRobin Murphy <robin.murphy@arm.com>
Fri, 25 Oct 2019 18:08:36 +0000 (19:08 +0100)
committerWill Deacon <will@kernel.org>
Mon, 4 Nov 2019 19:59:30 +0000 (19:59 +0000)
commit205577ab6f7ade6185f764ed78fb6875dca40205
tree3dc33876b1194b7d1cf1a384e7216659a6d95344tree | snapshot
parent5fb190b0b52552de880536d4f409c4300c25e3d4commit | diff
iommu/io-pgtable-arm: Rationalise MAIR handling

Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
drivers/iommu/arm-smmu-v3.c diff | blob | history
drivers/iommu/arm-smmu.c diff | blob | history
drivers/iommu/io-pgtable-arm.c diff | blob | history
drivers/iommu/ipmmu-vmsa.c diff | blob | history
drivers/iommu/qcom_iommu.c diff | blob | history
include/linux/io-pgtable.h diff | blob | history
Domain: System / Kernel;