ASoC: rsnd: merge SRC clock timing/setting

ASoC: rsnd: merge SRC clock timing/setting

SRC clock and timing setting register
exist in SRU and ADG on Gen1.
But, these are merged into ADG on Gen2.
Current driver is supporting Gen1 SRC only
at this point, but, above settings are
set as different function.
This patch merges these as preparation of Gen2 support.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 28dc4b63cdb96f2448a677320fcc0eb112e13e3f)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>