clk: sunxi: Add Allwinner A20 gates
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 25 Jul 2013 19:06:56 +0000 (21:06 +0200)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 26 Aug 2013 08:58:21 +0000 (10:58 +0200)
commit1fb2e4aab8b31b15e6be5debacb4203333360fd2
treeab19fee3cc118d0205aa5bcc937be601cd671381
parent6a721db180a22d8e2d59d864446309bc7a09c26f
clk: sunxi: Add Allwinner A20 gates

The Allwinner A20 is almost identical to the earlier A10 SoC from
Allwinner on many aspects, including the clocks tree. However, since the
A20 has some additionnal IPs compared to the A10, the clock tree isn't
exactly the same, especially when it comes to the gated clocks
available. We thus need to register different clock gates for the A20.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Emilio López <emilio@elopez.com.ar>
Documentation/devicetree/bindings/clock/sunxi.txt
Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt [new file with mode: 0644]
drivers/clk/sunxi/clk-sunxi.c