arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)
authorCatalin Marinas <catalin.marinas@arm.com>
Wed, 28 Feb 2018 18:47:20 +0000 (18:47 +0000)
committerWill Deacon <will.deacon@arm.com>
Tue, 6 Mar 2018 18:52:32 +0000 (18:52 +0000)
commit1f85b42a691cd8329ba82dbcaeec80ac1231b32a
treeda12a0975152204ecccb02c335e68cb3f09aed22
parent6b24442d68e78c57c8837920ea5dfb252571847a
arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)

Commit 97303480753e ("arm64: Increase the max granular size") increased
the cache line size to 128 to match Cavium ThunderX, apparently for some
performance benefit which could not be confirmed. This change, however,
has an impact on the network packets allocation in certain
circumstances, requiring slightly over a 4K page with a significant
performance degradation.

This patch reverts L1_CACHE_SHIFT back to 6 (64-byte cache line) while
keeping ARCH_DMA_MINALIGN at 128. The cache_line_size() function was
changed to default to ARCH_DMA_MINALIGN in the absence of a meaningful
CTR_EL0.CWG bit field.

In addition, if a system with ARCH_DMA_MINALIGN < CTR_EL0.CWG is
detected, the kernel will force swiotlb bounce buffering for all
non-coherent devices since DMA cache maintenance on sub-CWG ranges is
not safe, leading to data corruption.

Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Cc: Timur Tabi <timur@codeaurora.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm64/Kconfig
arch/arm64/include/asm/cache.h
arch/arm64/include/asm/dma-direct.h [new file with mode: 0644]
arch/arm64/kernel/cpufeature.c
arch/arm64/mm/dma-mapping.c
arch/arm64/mm/init.c