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author	Matt Arsenault <Matthew.Arsenault@amd.com>
	Mon, 4 Feb 2019 23:29:31 +0000 (23:29 +0000)
committer	Matt Arsenault <Matthew.Arsenault@amd.com>
	Mon, 4 Feb 2019 23:29:31 +0000 (23:29 +0000)
commit	1f795e2c2a0b81d71f69621649b21cb7b1e616b4
tree	81569a0ea2e7f49b2d86aafa5425248ee5a6bdeb	tree \| snapshot
parent	f2a26339e2bdd5a13982d21d21c0bdf1d37b9ab8	commit \| diff

GlobalISel: Enforce operand types for constants

A number of of tests were using imm operands, not cimm. Since CSE
relies on the exact ConstantInt* pointer used, and implicit
conversions are generally evil, also enforce the bitsize of the types.

llvm-svn: 353113

28 files changed:

llvm/lib/CodeGen/MachineVerifier.cpp		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir		diff \| blob \| history
llvm/test/Verifier/test_g_constant.mir		diff \| blob \| history
llvm/test/Verifier/test_g_fconstant.mir		diff \| blob \| history
llvm/test/Verifier/test_phis_precede_nonphis.mir		diff \| blob \| history

Domain: System / Toolchain;

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