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[DAGCombine] Improve ReduceLoad for SRL
authorSam Parker <sam.parker@arm.com>
Mon, 9 Apr 2018 08:16:11 +0000 (08:16 +0000)
committerSam Parker <sam.parker@arm.com>
Mon, 9 Apr 2018 08:16:11 +0000 (08:16 +0000)
commit1f4f4d9a080cc9ea27c1040ec1c7341a29d77487
tree83628e026317a5bebc4b9c22aea961c82269c974tree | snapshot
parent324edae831410c7d7e37d446656f948b36d2e56ccommit | diff
[DAGCombine] Improve ReduceLoad for SRL

Recommitting r329283, third time lucky...

If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.

Differential Revision: https://reviews.llvm.org/D41350

llvm-svn: 329551
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/test/CodeGen/ARM/shift-combine.ll diff | blob | history
llvm/test/CodeGen/PowerPC/trunc-srl-load.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/h-registers-1.ll diff | blob | history
Domain: System / Toolchain;