[AArch64][SVE] Implement isVScaleKnownToBeAPowerOfTwo

[AArch64][SVE] Implement isVScaleKnownToBeAPowerOfTwo

According to https://developer.arm.com/documentation/102105/ia-00/?lang=en

> Arm is making a retrospective change to the SVE architecture to remove
> the capability of selecting a non-power-of-two vector length in
> non-Streaming SVE as well as in Streaming SVE mode. Specific updates as
> a result of this change will be communicated in due course.

This patch implements the isVScaleKnownToBeAPowerOfTwo method to teach
DAG Combines that VScale will be known to be a power of 2, which helps
reduce or simplify some expressions (notably the udiv in vector trip
count expressions).

Differential Revision: https://reviews.llvm.org/D141486