anv: Use input assembly state only when pipeline has vertex stage
authorMarcin Ślusarz <marcin.slusarz@intel.com>
Tue, 31 Aug 2021 12:49:57 +0000 (14:49 +0200)
committerMarge Bot <eric+marge@anholt.net>
Mon, 4 Oct 2021 18:55:56 +0000 (18:55 +0000)
commit1f1ad5a9b43e1757e6603668b1266f29af2dba9c
tree7a71491a1f85640e8d1aff3d2f2168ca705b0673
parentd79c518a32b5d95ab300fbc765c3edad4cf517c5
anv: Use input assembly state only when pipeline has vertex stage

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13047>
src/intel/vulkan/anv_pipeline.c