[AMDGPU] Further reduce attaching of implicit operands to spills
authorJeffrey Byrnes <Jeffrey.Byrnes@amd.com>
Thu, 12 Jan 2023 01:06:48 +0000 (17:06 -0800)
committerJeffrey Byrnes <Jeffrey.Byrnes@amd.com>
Thu, 19 Jan 2023 22:31:07 +0000 (14:31 -0800)
commit1f08d3bc3a9a018534e52a47027dfb05cb4f55b3
treed911954c253b87c14f5b3a8fbcdab88f3fb30d8f
parent6b43568ff83f70cee9fd920f1781526f5b595de5
[AMDGPU] Further reduce attaching of implicit operands to spills

Extension of https://reviews.llvm.org/D141101 to even further reduce the amount of implicit operands we attach. The main benefit is to improve cability of post-ra scheduler, and reduce unneeded dependency resolution (e.g. inserting snops).

Unfortunately, we run into regressions if we completely minimize the amount implicit operands (naively), we run into some regressions (e.g. dual_movs are replaced with multiple calls to v_mov). This is even more reason to switch to LiveRegUnits.

Nonetheless, this patch removes the operands which we can for free (more or less).

Change-Id: Ib4f409202b36bdbc59eed615bc2d19fa8bd8c057

Differential Revision: https://reviews.llvm.org/D141557

Change-Id: I8b039e3c0d39436b384083f8beb947ee1b1730b2
21 files changed:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
llvm/test/CodeGen/AMDGPU/spill192.mir
llvm/test/CodeGen/AMDGPU/spill224.mir
llvm/test/CodeGen/AMDGPU/spill288.mir
llvm/test/CodeGen/AMDGPU/spill320.mir
llvm/test/CodeGen/AMDGPU/spill352.mir
llvm/test/CodeGen/AMDGPU/spill384.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill.mir