radeonsi: merge 2 conditional blocks with same condition into 1 in culling code
authorMarek Olšák <marek.olsak@amd.com>
Tue, 11 May 2021 15:47:10 +0000 (11:47 -0400)
committerMarge Bot <eric+marge@anholt.net>
Mon, 21 Jun 2021 19:03:29 +0000 (19:03 +0000)
commit1e9cc86511f154896d0bd3beab8b96c9d62d00f6
tree0e0577124132cb16d7fb1ac621f4d238bd4ab5d1
parent786678a017c5b488bd36fade440d9f5308c3d23c
radeonsi: merge 2 conditional blocks with same condition into 1 in culling code

The block only loads input VGPRs from LDS, and the next block uses them.
The entering condition is the same, even though the second block is
the next shader part beginning with the prolog.

Simply move the VGPR loads into the prolog.

This decreases the shader code size by 12 bytes.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11102>
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
src/gallium/drivers/radeonsi/si_shader.c
src/gallium/drivers/radeonsi/si_shader.h
src/gallium/drivers/radeonsi/si_shader_llvm.c
src/gallium/drivers/radeonsi/si_shader_llvm_vs.c