net/mlx5: EQ, Use the right place to store/read IRQ affinity hint
authorSaeed Mahameed <saeedm@mellanox.com>
Mon, 19 Nov 2018 18:52:31 +0000 (10:52 -0800)
committerLeon Romanovsky <leonro@mellanox.com>
Tue, 20 Nov 2018 18:05:59 +0000 (20:05 +0200)
commit1e86ace4c140fd5a693e266c9b23409358f25381
treeccd5aaaec802da813abf9b9b5c09ab8e12b07d3f
parentb02394aa75e3942bea8dac6efc7f1a179fbe011f
net/mlx5: EQ, Use the right place to store/read IRQ affinity hint

Currently the cpu affinity hint mask for completion EQs is stored and
read from the wrong place, since reading and storing is done from the
same index, there is no actual issue with that, but internal irq_info
for completion EQs stars at MLX5_EQ_VEC_COMP_BASE offset in irq_info
array, this patch changes the code to use the correct offset to store
and read the IRQ affinity hint.

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Reviewed-by: Leon Romanovsky <leonro@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/ethernet/mellanox/mlx5/core/main.c
include/linux/mlx5/driver.h