dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support
authorConor Dooley <conor.dooley@microchip.com>
Wed, 7 Jun 2023 20:28:30 +0000 (21:28 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 21 Jun 2023 14:45:18 +0000 (07:45 -0700)
commit1e5cae98e46d15f4dc7c675e1bd0ed2172ea181c
tree004ede69685f51eb90545dbdb236de98e104bbcb
parent7816ebc1ddd16b5cc95febb75f778bf88411a365
dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support

Similar to commit 41ebfc91f785 ("dt-bindings: riscv: explicitly mention
assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm
extensions also used to be part of the base ISA but were removed after
the bindings were merged. Document the assumption of their presence in
the base ISA.

Suggested-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230607-rerun-retinal-5e8ba89e98f1@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/riscv/cpus.yaml