cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
authorAnton Staaf <robotboy@chromium.org>
Mon, 17 Oct 2011 23:46:13 +0000 (16:46 -0700)
committerWolfgang Denk <wd@denx.de>
Sun, 23 Oct 2011 18:50:43 +0000 (20:50 +0200)
commit1e41f5ad455e75d3985a0e4670ba1338c2e8faca
tree48c3538f33268a49e35268dc9b05416e1995d050
parent3620f860eff02722aa559e568f4ca87f4c304901
cache: include asm/cache.h for ARCH_DMA_MINALIGN definition

ARCH_DMA_MINALIGN will be used to allocate DMA buffers that are
aligned correctly.  In all current cases this means that the DMA
buffer will be aligned to at least the L1 data cache line size of
the configured architecture.  If the board configuration file
does not specify the architecture L1 data cache line size then the
maximum line size of the architecture is used to align DMA buffers.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Laurence Withers <lwithers@guralp.com>
include/common.h