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(parent: 639eb92) | patch
clk: imx5: Fix i.MX50 ESDHC clock registers
authorJonathan Neuschäfer <j.neuschaefer@gmx.net>
Tue, 26 Mar 2019 18:22:58 +0000 (19:22 +0100)
committerShawn Guo <shawnguo@kernel.org>
Wed, 3 Apr 2019 09:10:06 +0000 (16:10 +0700)
commit1e06250983b132fe5d93e812e2ede05eb234e5a8
tree1d4b2da11ddab0b2ffc7834c713b47f175e876bdtree | snapshot
parent639eb92531166a17bdb459437fbadf97459c5370commit | diff
clk: imx5: Fix i.MX50 ESDHC clock registers

The MUX bits for esdhc_{a,c,d}_sel are shifted by one bit within CSCMR1,
because esdhc_b_sel (ESDHC3_CLK_SEL in the Reference Manual) is extended
by one bit.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx51-imx53.c diff | blob | history
Domain: System / Kernel;