mtd: rawnand: denali: optimize timing parameters for data interface
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Fri, 22 Jun 2018 16:06:38 +0000 (01:06 +0900)
committerMiquel Raynal <miquel.raynal@bootlin.com>
Wed, 18 Jul 2018 07:24:14 +0000 (09:24 +0200)
commit1dfac31a5a63ac04a9b5fbc3f5105a586560f191
treee186e6351b8f56d2f58ec0dbda6d4b0d9e43b1de
parent6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5
mtd: rawnand: denali: optimize timing parameters for data interface

This commit improves the ->setup_data_interface() hook.

The denali_setup_data_interface() needs the frequency of clk_x
and the ratio of clk_x / clk.

The latter is currently hardcoded in the driver, like this:

  #define DENALI_CLK_X_MULT       6

The IP datasheet requires that clk_x / clk be 4, 5, or 6.  I just
chose 6 because it is the most defensive value, but it is not optimal.
By getting the clock rate of both "clk" and "clk_x", the driver can
compute the timing values more precisely.

To not break the existing platforms, the fallback value, 50 MHz is
provided.  It is true for all upstreamed platforms.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Richard Weinberger <richard@nod.at>
Tested-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
drivers/mtd/nand/raw/denali.c
drivers/mtd/nand/raw/denali.h
drivers/mtd/nand/raw/denali_dt.c
drivers/mtd/nand/raw/denali_pci.c