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(parent: cdaf1df) | patch
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
authorDerek Schuff <dschuff@google.com>
Mon, 4 Apr 2016 17:09:25 +0000 (17:09 +0000)
committerDerek Schuff <dschuff@google.com>
Mon, 4 Apr 2016 17:09:25 +0000 (17:09 +0000)
commit1dbf7a571f39c07d8c301ffa29bb9c27d8417539
tree1112ae62d73ab1c5efa0b5b0cd4f15335c6cae5btree | snapshot
parentcdaf1df6579f0b932db4f4a29b176bab74305ae5commit | diff
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes

Summary:
This adds the same checks that were added in r264593 to all
target-specific passes that run after register allocation.

Reviewers: qcolombet

Subscribers: jyknight, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18525

llvm-svn: 265313
45 files changed:
llvm/lib/CodeGen/ExecutionDepsFix.cpp diff | blob | history
llvm/lib/CodeGen/IfConversion.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64CollectLOH.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp diff | blob | history
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp diff | blob | history
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp diff | blob | history
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp diff | blob | history
llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp diff | blob | history
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp diff | blob | history
llvm/lib/Target/ARM/Thumb2SizeReduction.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonGenMux.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp diff | blob | history
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp diff | blob | history
llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp diff | blob | history
llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp diff | blob | history
llvm/lib/Target/Lanai/LanaiSetflagAluCombiner.cpp diff | blob | history
llvm/lib/Target/MSP430/MSP430BranchSelector.cpp diff | blob | history
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp diff | blob | history
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp diff | blob | history
llvm/lib/Target/Mips/MipsHazardSchedule.cpp diff | blob | history
llvm/lib/Target/Mips/MipsLongBranch.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp diff | blob | history
llvm/lib/Target/Sparc/DelaySlotFiller.cpp diff | blob | history
llvm/lib/Target/SystemZ/SystemZElimCompare.cpp diff | blob | history
llvm/lib/Target/SystemZ/SystemZLongBranch.cpp diff | blob | history
llvm/lib/Target/SystemZ/SystemZShortenInst.cpp diff | blob | history
llvm/lib/Target/X86/X86ExpandPseudo.cpp diff | blob | history
llvm/lib/Target/X86/X86FixupBWInsts.cpp diff | blob | history
llvm/lib/Target/X86/X86FixupLEAs.cpp diff | blob | history
llvm/lib/Target/X86/X86FloatingPoint.cpp diff | blob | history
llvm/lib/Target/X86/X86PadShortFunction.cpp diff | blob | history
llvm/lib/Target/X86/X86VZeroUpper.cpp diff | blob | history
llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp diff | blob | history
llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir diff | blob | history
Domain: System / Toolchain;