perf/x86/intel: Fix instructions:ppp support in Sapphire Rapids
authorKan Liang <kan.liang@linux.intel.com>
Fri, 18 Jun 2021 15:12:54 +0000 (08:12 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Wed, 23 Jun 2021 16:30:55 +0000 (18:30 +0200)
commit1d5c7880992a06679585e7e568cc679c0c5fd4f2
tree96c6af4ccdf804d9a0615e5440ab6870d752dbac
parentd18216fafecf2a3a7c2b97086892269d6ab3cd5e
perf/x86/intel: Fix instructions:ppp support in Sapphire Rapids

Perf errors out when sampling instructions:ppp.

$ perf record -e instructions:ppp -- true
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument)
for event (instructions:ppp).

The instruction PDIR is only available on the fixed counter 0. The event
constraint has been updated to fixed0_constraint in
icl_get_event_constraints(). The Sapphire Rapids codes unconditionally
error out for the event which is not available on the GP counter 0.

Make the instructions:ppp an exception.

Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Reported-by: Yasin, Ahmad <ahmad.yasin@intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1624029174-122219-4-git-send-email-kan.liang@linux.intel.com
arch/x86/events/intel/core.c