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(parent: 9d009d9) | patch
phy: ti-pipe3: Fix PCIe power up sequence
authorRoger Quadros <rogerq@ti.com>
Fri, 22 Mar 2019 08:58:07 +0000 (10:58 +0200)
committerKishon Vijay Abraham I <kishon@ti.com>
Wed, 17 Apr 2019 08:43:07 +0000 (14:13 +0530)
commit1d1bae7250758904ab09458022e2d97c23cf42b7
treee4c8d151baca857511c56254c40ff963071f3fe3tree | snapshot
parent9d009d9c20624cd8ed2a3ae0e43752c4a34b4893commit | diff
phy: ti-pipe3: Fix PCIe power up sequence

TRM [1] mentions that we need to power up
PCIESS_PHY_TX and PCIESS_PHY_RX before configuring
PCIe_PHY_RX SCP settings.

See "Table 26-81. PCIePHY Subsystem Low-Level Programming Sequence".

[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers/phy/ti/phy-ti-pipe3.c diff | blob | history
Domain: System / Kernel;