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(parent: 755674b) | patch
OpaquePtr: Update more tests to use typed sret
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 21 Nov 2020 00:02:42 +0000 (19:02 -0500)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 21 Nov 2020 01:08:43 +0000 (20:08 -0500)
commit1d1234b2a4286eebb89ea5e9796098f308c553d2
treeed6df71be912013c6121a515ca671b44d99b9b30tree | snapshot
parent755674b715b1cb1d1d7d2753a6fd42104cf10cb9commit | diff
OpaquePtr: Update more tests to use typed sret
34 files changed:
llvm/test/Analysis/Lint/noalias-byval.ll diff | blob | history
llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll diff | blob | history
llvm/test/Assembler/sret-type-attr.ll diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll diff | blob | history
llvm/test/CodeGen/AArch64/swiftself.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/call-argument-types.ll diff | blob | history
llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll diff | blob | history
llvm/test/CodeGen/ARM/interval-update-remat.ll diff | blob | history
llvm/test/CodeGen/ARM/swiftself.ll diff | blob | history
llvm/test/CodeGen/Hexagon/calling-conv-2.ll diff | blob | history
llvm/test/CodeGen/Hexagon/calling-conv.ll diff | blob | history
llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll diff | blob | history
llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll diff | blob | history
llvm/test/CodeGen/Hexagon/regscavengerbug.ll diff | blob | history
llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll diff | blob | history
llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll diff | blob | history
llvm/test/CodeGen/PowerPC/resolvefi-basereg.ll diff | blob | history
llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll diff | blob | history
llvm/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll diff | blob | history
llvm/test/CodeGen/Thumb2/constant-islands.ll diff | blob | history
llvm/test/CodeGen/X86/combine-sbb.ll diff | blob | history
llvm/test/CodeGen/X86/misched-aa-colored.ll diff | blob | history
llvm/test/CodeGen/X86/movtopush.ll diff | blob | history
llvm/test/CodeGen/X86/negate-add-zero.ll diff | blob | history
llvm/test/CodeGen/X86/preallocated.ll diff | blob | history
llvm/test/CodeGen/X86/scev-interchange.ll diff | blob | history
llvm/test/CodeGen/X86/win32_sret.ll diff | blob | history
llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll diff | blob | history
llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/combined-partial-overwrites.ll diff | blob | history
llvm/test/Transforms/IndVarSimplify/interesting-invoke-use.ll diff | blob | history
llvm/test/Transforms/InstCombine/insert-val-extract-elem.ll diff | blob | history
llvm/test/Transforms/MemCpyOpt/memcpy.ll diff | blob | history
llvm/test/Transforms/MemCpyOpt/sret.ll diff | blob | history
llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll diff | blob | history
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