ARM: DRA7: clockdomain: Implement timer workaround for errata i874
authorKeerthy <j-keerthy@ti.com>
Tue, 5 Apr 2016 21:44:12 +0000 (16:44 -0500)
committerPaul Walmsley <paul@pwsan.com>
Sun, 10 Apr 2016 17:43:57 +0000 (11:43 -0600)
commit1cbabcb9807e31e87ef3a12af76ea025ceb582d3
treeb4e016f74a2405666d3165fd5db411887144e0d3
parent3ca4a238106dedc285193ee47f494a6584b6fd2f
ARM: DRA7: clockdomain: Implement timer workaround for errata i874

Errata Title:
i874: TIMER5/6/7/8 interrupts not propagated

Description:
When TIMER5, TIMER6, TIMER7, or TIMER8 clocks are enabled
(CM_IPU_TIMER5/6/7/8_CLKCTRL[0:1]MODULEMODE=0x2:ENABLE) and the CD-IPU
is in HW_AUTO mode (CM_IPU_CLKSTCTRL[0:1]CLKTRCTRL=0x3:HW_AUTO) the
corresponding TIMER will continue counting, but enabled interrupts
will not be propagated to the destinations (MPU, DSP, etc) in the
SoC until the TIMER registers are accessed from the CPUs (MPU, DSP
etc.). This can result in missed timer interrupts.

Workaround:
In order for TIMER5/6/7/8 interrupts to be propagated and serviced
correctly the CD_IPU domain should be set to SW_WKUP mode
(CM_IPU_CLKSTCTRL[0:1]CLKTRCTRL=0x2:SW_WKUP).

The above workaround is achieved by switching the IPU clockdomain
flags from HWSUP_SWSUP to SWSUP only.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/clockdomains7xx_data.c