drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is down
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 18 Feb 2016 19:54:26 +0000 (21:54 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 22 Feb 2016 17:28:04 +0000 (19:28 +0200)
commit1ca993d237a587be19dd58cfe27f1e9093291320
tree844fcee8d567f2fd36693bd3f0f55ffea3f7b386
parent1e657ad7a48f1ce5005dfa570749f8e78f06ff44
drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is down

PIPESTAT registers live in the display power well on VLV/CHV, so we
shouldn't access them when things are powered down. Let's check
whether the display interrupts are on or off before accessing the
PIPESTAT registers.

Another option would be to read the PIPESTAT registers only when
the IIR register indicates that there's a pending pipe event. But
that would mean we might miss even more underrun reports than we
do now, because the underrun status bit lives in PIPESTAT but doesn't
actually generate an interrupt.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93738
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455825266-24686-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
drivers/gpu/drm/i915/i915_irq.c