[mips] Remap move as or.
authorVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>
Tue, 11 Aug 2015 08:56:25 +0000 (08:56 +0000)
committerVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>
Tue, 11 Aug 2015 08:56:25 +0000 (08:56 +0000)
commit1c78ca6a09cec862d6aad04e820dae98b71be9fc
treeef6def2a0475fbea2672cf161260dc2830857755
parent7337ee23d8ee9864d6b5f4140aaa56cf68388361
[mips] Remap move as or.

Summary:
This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.

This patch preserves the disassembly behaviour so that disassembling a old style
(d)addu move still appears as move, but assembling move always gives an or

Patch by Simon Dardis.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11796

llvm-svn: 244579
47 files changed:
llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/lib/Target/Mips/Mips64InstrInfo.td
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/lib/Target/Mips/MipsInstrInfo.td
llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
llvm/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
llvm/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
llvm/test/MC/Disassembler/Mips/mips32_le.txt
llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
llvm/test/MC/Mips/mips-alu-instructions.s
llvm/test/MC/Mips/mips1/valid.s
llvm/test/MC/Mips/mips2/valid.s
llvm/test/MC/Mips/mips3/valid.s
llvm/test/MC/Mips/mips32/valid.s
llvm/test/MC/Mips/mips32r2/valid.s
llvm/test/MC/Mips/mips32r3/valid.s
llvm/test/MC/Mips/mips32r5/valid.s
llvm/test/MC/Mips/mips32r6/valid.s
llvm/test/MC/Mips/mips4/valid.s
llvm/test/MC/Mips/mips5/valid.s
llvm/test/MC/Mips/mips64-alu-instructions.s
llvm/test/MC/Mips/mips64/valid.s
llvm/test/MC/Mips/mips64r2/valid.s
llvm/test/MC/Mips/mips64r3/valid.s
llvm/test/MC/Mips/mips64r5/valid.s
llvm/test/MC/Mips/mips64r6/valid.s