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(parent: d244a25) | patch
radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING
authorMarek Olšák <marek.olsak@amd.com>
Tue, 7 Jul 2020 03:51:25 +0000 (23:51 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 22 Jul 2020 16:08:19 +0000 (12:08 -0400)
commit1c6eca23fdd8bc112c70914100601d0e382a8154
tree4b74e949b02b3737d0eafdece9abf1f55a369665tree | snapshot
parentd244a25c072557edd1133356b94557938c000f78commit | diff
radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING

Copied from PAL. Higher values break tessellation, which I was only able
to reproduce with register shadowing enabled.

Fixes: 0bf3e6fae7f82b4f16fbcbb05a1ae47f7930e189 "radeonsi/gfx10: double the number of tessellation offchip buffers per SE"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
src/gallium/drivers/radeonsi/si_pipe.c diff | blob | history
Domain: Graphics System / GL;