clk:starfive:Count PLL1 rate
authorXingyu Wu <xingyu.wu@starfivetech.com>
Mon, 24 Oct 2022 10:20:54 +0000 (18:20 +0800)
committerXingyu Wu <xingyu.wu@starfivetech.com>
Wed, 26 Oct 2022 09:47:33 +0000 (17:47 +0800)
commit1c6b87ca5298358b0fa4226fc624605aa6163e68
treee62ace53da6f224aba7c8d2e51cf4a9c91ed61b1
parent2577c2b760ff5b7c394ece88e947229803cf9dff
clk:starfive:Count PLL1 rate

Count PLL1 rate through reading syscon registers.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-pll.c [changed mode: 0755->0644]
drivers/clk/starfive/clk-starfive-jh7110-sys.c [changed mode: 0755->0644]