drm/radeon: align VM PTBs (Page Table Blocks) to 32K
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 12 Jul 2013 19:56:02 +0000 (15:56 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 15 Jul 2013 13:37:10 +0000 (09:37 -0400)
commit1c01103cb90197900beb534911de558d7a43d0b3
tree55a3b1e0bd4ea45f884577d91eaba293567ee95d
parent6c4f978b357bc779c703fda1f200e9179623d3e9
drm/radeon: align VM PTBs (Page Table Blocks) to 32K

Covers requirements of all current asics.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_gart.c