clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
authorChen-Yu Tsai <wens@csie.org>
Wed, 5 Dec 2018 10:11:51 +0000 (18:11 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 12 Feb 2019 18:47:05 +0000 (19:47 +0100)
commit1bf188456312d9babfdb7fe25756653beeddf0ea
treea63b995f1206c7a78981a914608e8c4433c72dde
parent322a53b8f9b0e12e535b644322ce3b306155c19d
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks

[ Upstream commit 6e6da2039c82271dd873b9ad2b902a692a7dd554 ]

All the audio interfaces on Allwinner SoCs need to change their module
clocks during operation, to switch between support for 44.1 kHz and 48
kHz family sample rates. The clock rate for the module clocks is
governed by their upstream audio PLL. The module clocks themselves only
have a gate, and sometimes a divider or mux. Thus any rate changes need
to be propagated upstream.

Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve
this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/sunxi-ng/ccu-sun8i-a33.c