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(parent: a615d0b) | patch
ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration
authorNishanth Menon <nm@ti.com>
Mon, 27 Jul 2015 21:26:06 +0000 (16:26 -0500)
committerTom Rini <trini@konsulko.com>
Thu, 13 Aug 2015 00:47:50 +0000 (20:47 -0400)
commit1bbb556a6a5c0f44d2da32700fce4d279c851e9f
tree14d79050cbb4c40d8f5ef4a285d8decac0cf0c36tree | snapshot
parenta615d0be6a73fc48a22e5662608260fe9b9149ffcommit | diff
ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration

Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm/cpu/armv7/omap5/hwinit.c diff | blob | history
arch/arm/include/asm/arch-omap5/sys_proto.h diff | blob | history
Domain: System / Kernel;