Generate proper DWARF reg num for ARM32 (#57443)

Generate proper DWARF reg num for ARM32 (#57443)

After introduction of VFP-v3 ARM S0-S31 no longer can be generated using LLVM because  numbering of registers to start from 256 and only D0-D31 are used.
So this change encode S0 as D0, S2 as D1, etc. Also use reg nums for DXX registers.
This change fix generation of CFI codes,
which trigger issue with generation of DWARF using LLVM in NativeAOT
See https://developer.arm.com/documentation/ihi0040/c/?lang=en#dwarf-register-names
See https://github.com/dotnet/runtimelab/issues/1388